Final Update Posted for Z14 Hardware Support

I have just published Z22-1711B that adds support in z/XDC for all the rest of the new machine instructions introduced on IBM’s Z14 hardware. All of the new opcodes, the new mnemonics and the new extended mnemonics are now recognized and understood.

Since many of the new instructions are vector instructions, I took the opportunity to review the existing support. I did find a few errors that I corrected, and I added support for a handful of instructions that I had previously missed.

One interesting thing about extended mnemonics is that they can be viewed as machine instructions having opcodes longer than two bytes. This is because most of them coerce specific values in various operand nibbles. For example, the LLHFR instruction can be considered as being in instruction whose opcode is five bytes long!

LLHFR is an extended mnemonic for the RISBLGZ instruction. Specifically, LLHFR is a shortcut name for RISBLGZ R1,R2,0,31,32. So LLHFR’s “opcode” is:

  • EC in the instruction’s 1st byte.
  • 51 in the instruction’s 6th byte.
  • 9F in the instruction’s 4th byte.
  • 00 in the instruction’s 3rd byte.
  • 20 in the instruction’s 5th byte.

Previously, z/XDC’s tables supported only opcodes up to four bytes long. Now, It will support opcodes up to the full length of the instruction – six bytes. There aren’t any 6-byte opcodes yet (that I know of), but there are quite a number of 5-byte opcodes.

And then there’s VNOT, a particularly strange beast. Whereas all other extended mnemonics coerce specific values in specific operand positions, VNOT follows a different road. It is defined in terms of the RELATIONSHIP amongst its operands, not their values.

VNOT is an extended mnemonic for the VNO V1,V2,V3 instruction. Specifically, VNOT is any VNO instruction where the V2 and V3 registers are the same register. Wow! This means that there are, in effect, 32 distinct VNOT instructions. And z/XDC now supports all 32 of them!

Maybe I’m weird, but it’s been fun!